COMPSYS 305 Digital Systems Design - Course Outlines

Course Prescription

Digital Systems implementation technologies with emphasis on hardware description languages and design abstraction levels; structural, architectural and behavioural modelling; register-transfer level design; datapath and control units; functional and timing simulations; FPGA-based implementation design flow and case studies.

Course Overview

Introduction to digital system design

Trends in design and implementation of digital systems, levels of design abstraction, design flow and implementation technologies are discussed. Field Programmable Gate Arrays (FPGA) as the prototyping and implementation technology are introduced.

Introduction to VHDL

Modelling of simple digital systems using hardware description language constructs and discrete event simulation tools are discussed. Functional and timing simulations with proper testbenches are covered. Issues in logic synthesis are introduced and relationship between VHDL constructs and synthesizable circuits will be discussed.

Techniques and approaches for design of digital systems

Systematic approaches to design digital systems on register-transfer level (RTL), including finite state machine, datapaths, wired and microprogrammed control and pipelined implementation are introduced.

Case studies including designing device interfaces (PS/2 mouse, PS/2 keyboard, VGA display), generating simple graphics and some other examples are considered.

Implementation of Digital systems

The synthesis issues and how to apply timing constraints at the time of implementation are considered in more details. Some advanced features of FPGAs for implementation of digital systems will be introduced.

Tools:

Modelsim (https://eda.sw.siemens.com/en-US/ic/modelsim/)
Intel (Altera) Quartus II 18.1 or newer version if applicable.
FPGA development board (DE0-CV board)

Course Requirements

Prerequisite: COMPSYS 201

Learning Outcomes

By the end of this course, students will be able to:

Use and apply principles and techniques of modern digital systems design which ranges from medium to large scale digital systems (Capability 3.1, 3.2 and 5.1)
Use modern design methodology based on a hardware description language (VHDL) to design complex digital systems (Capability 3.1, 3.2 and 5.1)
Design digital systems using register transfer level (RTL) methodology where there is clear distinguishing between data processing and control part of systems (Capability 4.2 and 5.1)
Apply the systematic design flow from the digital system design specification to the implementation, where the target technology will be field-programmable gate arrays (FPGAs) (Capability 3.1, 3.2, 4.1, 4.2 and 5.1)
Analyse the important architectural components such as memory and clock networks of FPGA, extract design parameters, evaluate them and apply design trade-offs for the application (Capability 4.1, 4.2 and 5.1)
Verify digital systems functionality using simulation and testbenches before real implementation (Capability 3.2, 4.2, 5.1 and 7.1)
Use the specifications of programmable reconfigurable devices and select the appropriate device for the application in hand and prototype medium scale digital systems based on FPGA technology. (Capability 3.1, 3.2, 6.1 and 7.1)
Design and implement a digital system prototype using electronic design automation (EDA) tools and FPGAs (as a team work) considering the resource usage and timing requirements. (Capability 3.2, 5.1, 6.1 and 7.1)
Demonstrate effective collaboration as a team to complete a group project by setting clear goals and distributing tasks between the team members. Present the final design demo and report. (Capability 6.1 and 7.1)

Assessments

Assessment Type	Percentage	Classification
Laboratories	10%	Individual Coursework
Test	25%	Individual Coursework
Mini-Project	30%	Group Coursework
Final Exam	35%	Individual Coursework
4 types	100%

Assessment Type	Learning Outcome Addressed
	1	2	3	4	5	6	7	8	9
Laboratories
Test
Mini-Project
Final Exam

Workload Expectations

This course is a standard 15 point course and students are expected to spend 10 hours per week involved in each 15 point course that they are enrolled in.

For this course, you can expect 24 hours of lectures, 16 hours instructed lab sessions and 80 hours of working on lab assignments, test preparation and mini-projects.

Delivery Mode

Campus Experience

Attendance is required at scheduled activities including labs to receive credit for components of the course.
Lectures will be available as recordings. Other learning activities including labs will not be available as recordings.
The course will not include live online events including group discussions.
Attendance on campus is required for the test and lab sessions.
The activities for the course are scheduled as a standard weekly timetable.

Learning Resources

Course materials are made available in a learning and collaboration tool called Canvas which also includes reading lists and lecture recordings (where available).

Please remember that the recording of any class on a personal device requires the permission of the instructor.

Health & Safety

Health and safety conditions when using MDLS and/or ECSE research labs require certificate of passing induction training. Further, students are expected to adhere to the guidelines outlined in the Health and Safety section of the Engineering Undergraduate Handbook.

Student Feedback

At the end of every semester students will be invited to give feedback on the course and teaching through a tool called SET or Qualtrics. The lecturers and course co-ordinators will consider all feedback and respond with summaries and actions.

Your feedback helps teachers to improve the course and its delivery for future students.

Class Representatives in each class can take feedback to the department and faculty staff-student consultative committees.

Academic Integrity

The University of Auckland will not tolerate cheating, or assisting others to cheat, and views cheating in coursework as a serious academic offence. The work that a student submits for grading must be the student's own work, reflecting their learning. Where work from other sources is used, it must be properly acknowledged and referenced. This requirement also applies to sources on the internet. A student's assessed work may be reviewed for potential plagiarism or other forms of academic misconduct, using computerised detection mechanisms.

Class Representatives

Class representatives are students tasked with representing student issues to departments, faculties, and the wider university. If you have a complaint about this course, please contact your class rep who will know how to raise it in the right channels. See your departmental noticeboard for contact details for your class reps.

Inclusive Learning

All students are asked to discuss any impairment related requirements privately, face to face and/or in written form with the course coordinator, lecturer or tutor.

Student Disability Services also provides support for students with a wide range of impairments, both visible and invisible, to succeed and excel at the University. For more information and contact details, please visit the Student Disability Services’ website http://disability.auckland.ac.nz

Special Circumstances

If your ability to complete assessed coursework is affected by illness or other personal circumstances outside of your control, contact a member of teaching staff as soon as possible before the assessment is due.

If your personal circumstances significantly affect your performance, or preparation, for an exam or eligible written test, refer to the University’s aegrotat or compassionate consideration page https://www.auckland.ac.nz/en/students/academic-information/exams-and-final-results/during-exams/aegrotat-and-compassionate-consideration.html.

This should be done as soon as possible and no later than seven days after the affected test or exam date.

Learning Continuity

In the event of an unexpected disruption, we undertake to maintain the continuity and standard of teaching and learning in all your courses throughout the year. If there are unexpected disruptions the University has contingency plans to ensure that access to your course continues and course assessment continues to meet the principles of the University’s assessment policy. Some adjustments may need to be made in emergencies. You will be kept fully informed by your course co-ordinator/director, and if disruption occurs you should refer to the university website for information about how to proceed.

Student Charter and Responsibilities

The Student Charter assumes and acknowledges that students are active participants in the learning process and that they have responsibilities to the institution and the international community of scholars. The University expects that students will act at all times in a way that demonstrates respect for the rights of other students and staff so that the learning environment is both safe and productive. For further information visit Student Charter https://www.auckland.ac.nz/en/students/forms-policies-and-guidelines/student-policies-and-guidelines/student-charter.html.

Disclaimer

Elements of this outline may be subject to change. The latest information about the course will be available for enrolled students in Canvas.

In this course students may be asked to submit coursework assessments digitally. The University reserves the right to conduct scheduled tests and examinations for this course online or through the use of computers or other electronic devices. Where tests or examinations are conducted online remote invigilation arrangements may be used. In exceptional circumstances changes to elements of this course may be necessary at short notice. Students enrolled in this course will be informed of any such changes and the reasons for them, as soon as possible, through Canvas.

Capability 3:	Knowledge and Practice
Capability 4:	Critical Thinking
Capability 5:	Solution Seeking
Capability 6:	Communication
Capability 7:	Collaboration

COMPSYS 305 : Digital Systems Design

Engineering

2024 Semester One (1243) (15 POINTS)