MECHENG 371 Digital Circuit Design - Course Outlines

Course Prescription

Fundamental concepts in the design of combinational and sequential logic circuits. Modern approach to design using CAD tools that exploit the advantage of automation. Students will be exposed to the use of FPGA to rapid prototype digital systems using schematic and hardware description language entries.

Course Overview

Topics covered are :-

1. Combinational and sequential logic circuit design: The student will be able to synthesize the required circuit based on the given requirements. They will be able to apply the design into a programmable logic device and then analyse and evaluate the performance and operation of the circuit.

2. Verilog HDL: The student will be able to use Quartus II as a design tool to enter the digital design using Verilog HDL entry. They will be able to simulate the Verilog HDL entry against design requirements and synthesize the design and test the performance in a FPGA.

3.Finite state machine design: Use of Quartus II to enter the design using Verilog HDL. Analyse the entered design using the simulation features of Quartus II, synthesize the design and evaluate the design into a targeted FPGA.

Course Requirements

Prerequisite: ELECTENG 101

Learning Outcomes

By the end of this course, students will be able to:

Design and implement combinational and sequential logic circuit with the aid of Boolean algebra, Karnaugh map and tabular minimization techniques, etc. (Capability 3.1 and 3.2)
Design and implement combinational logic circuits using Verilog HDL, then synthesize, simulate, and test its performances in an FPGA. (Capability 3.1 and 3.2)
Design and implement finite state machines with Verilog HDL, then synthesize, simulate and test its performances in an FPGA. (Capability 3.1 and 3.2)

Assessments

Assessment Type	Percentage	Classification
Assignments	30%	Group & Individual Coursework
Test	20%	Individual Test
Final Exam	50%	Individual Examination
3 types	100%

Assessment Type	Learning Outcome Addressed
	1	2	3
Assignments
Test
Final Exam

Workload Expectations

This course is a standard 15 point course and students are expected to spend 10 hours per week involved in each 15 point course that they are enrolled in.

For each week of this course, you can expect 3 hours of lectures, a 1 hour tutorial, 2 hours of reading and thinking about the content and 4 hours of work on assignments and/or for test preparation.

Delivery Mode

Campus Experience

Attendance is required at scheduled labs to complete components of the course.
Lectures will be available as recordings. Tutorials will also be available as recordings.
Attendance on campus is required for the test.
The activities for the course are scheduled as a standard weekly timetable.

Learning Resources

Course materials are made available in a learning and collaboration tool called Canvas which also includes reading lists and lecture recordings (where available).

Please remember that the recording of any class on a personal device requires the permission of the instructor.

Course notes in power point.

Most of the course materials are based on Fundamentals of Digital Logic with Verilog Design, 3/e by Stephen Brown and Zvonko Vranesic, ISBN: 0073380547

Health & Safety

All students are expected to compete the H&S for the related labs before being allowed to use the labs.

Students are expected to adhere to the guidelines outlined in the Health and Safety section of the Engineering Undergraduate Handbook.

Student Feedback

At the end of every semester students will be invited to give feedback on the course and teaching through a tool called SET or Qualtrics. The lecturers and course co-ordinators will consider all feedback and respond with summaries and actions.

Your feedback helps teachers to improve the course and its delivery for future students.

Class Representatives in each class can take feedback to the department and faculty staff-student consultative committees.

Learning objectives and content organisation will be made more clearly to ensure students understand what can be expected from this course.

Academic Integrity

The University of Auckland will not tolerate cheating, or assisting others to cheat, and views cheating in coursework as a serious academic offence. The work that a student submits for grading must be the student's own work, reflecting their learning. Where work from other sources is used, it must be properly acknowledged and referenced. This requirement also applies to sources on the internet. A student's assessed work may be reviewed for potential plagiarism or other forms of academic misconduct, using computerised detection mechanisms.

Class Representatives

Class representatives are students tasked with representing student issues to departments, faculties, and the wider university. If you have a complaint about this course, please contact your class rep who will know how to raise it in the right channels. See your departmental noticeboard for contact details for your class reps.

Inclusive Learning

All students are asked to discuss any impairment related requirements privately, face to face and/or in written form with the course coordinator, lecturer or tutor.

Student Disability Services also provides support for students with a wide range of impairments, both visible and invisible, to succeed and excel at the University. For more information and contact details, please visit the Student Disability Services’ website http://disability.auckland.ac.nz

Special Circumstances

If your ability to complete assessed coursework is affected by illness or other personal circumstances outside of your control, contact a member of teaching staff as soon as possible before the assessment is due.

If your personal circumstances significantly affect your performance, or preparation, for an exam or eligible written test, refer to the University’s aegrotat or compassionate consideration page https://www.auckland.ac.nz/en/students/academic-information/exams-and-final-results/during-exams/aegrotat-and-compassionate-consideration.html.

This should be done as soon as possible and no later than seven days after the affected test or exam date.

Learning Continuity

In the event of an unexpected disruption, we undertake to maintain the continuity and standard of teaching and learning in all your courses throughout the year. If there are unexpected disruptions the University has contingency plans to ensure that access to your course continues and course assessment continues to meet the principles of the University’s assessment policy. Some adjustments may need to be made in emergencies. You will be kept fully informed by your course co-ordinator/director, and if disruption occurs you should refer to the university website for information about how to proceed.

Student Charter and Responsibilities

The Student Charter assumes and acknowledges that students are active participants in the learning process and that they have responsibilities to the institution and the international community of scholars. The University expects that students will act at all times in a way that demonstrates respect for the rights of other students and staff so that the learning environment is both safe and productive. For further information visit Student Charter https://www.auckland.ac.nz/en/students/forms-policies-and-guidelines/student-policies-and-guidelines/student-charter.html.

Disclaimer

Elements of this outline may be subject to change. The latest information about the course will be available for enrolled students in Canvas.

In this course students may be asked to submit coursework assessments digitally. The University reserves the right to conduct scheduled tests and examinations for this course online or through the use of computers or other electronic devices. Where tests or examinations are conducted online remote invigilation arrangements may be used. In exceptional circumstances changes to elements of this course may be necessary at short notice. Students enrolled in this course will be informed of any such changes and the reasons for them, as soon as possible, through Canvas.

MECHENG 371 : Digital Circuit Design

Engineering

2024 Semester Two (1245) (15 POINTS)